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An Efficient Implementation of Advanced Encryption Standard on the Coarse-grained Reconfigurable Architecture

Kiem Hung Nguyen and Xuan Tu Tran (2016) An Efficient Implementation of Advanced Encryption Standard on the Coarse-grained Reconfigurable Architecture. VNU Journal of Computer Science and Communication Engineering, 32 (2). ISSN 0866-8612

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Abstract

The Advanced Encryption Standard (AES) is currently considered as one of the best symmetric-key block ciphers. The hardware implementation of the AES for hand-held mobile devices or wireless sensor network nodes is always required to meet the strict constraints in terms of performance, power and cost. Coarse-grained reconfigurable architectures are recently proposed as the solution that provides high flexibility, high performance and low power consumption for the next-generation embedded systems. This paper presents a flexible, high-performance implementation of the AES algorithm on a coarse-grained reconfigurable architecture, called MUSRA (Multimedia Specific Reconfigurable Architecture). First, we propose a hardware-software partitioning method for mapping the AES algorithm onto the MUSRA. Second, the parallel and pipelining techniques are considered thoughtfully to increase total computing throughput by efficiently utilizing the computing resources of the MUSRA. Some optimizations at both loop transformation level and scheduling level are performed in order to make better use of instruction-, loop- and task- level parallelism. The proposed implementation has been evaluated by the cycle-accurate simulator of the MUSRA. Experimental results show that the MUSRA can be reconfigured to support both encryption and decryption with all key lengths specified in the AES standard. The performance of the AES algorithm on the MUSRA is better than that of the ADRES reconfigurable processor, Xilinx Virtex-II, and the TI C64+ DSP.

Item Type:Article
Subjects:Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions:Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SIS Lab)
ID Code:1484
Deposited By: Prof. Xuan-Tu Tran
Deposited On:15 Feb 2016 02:55
Last Modified:17 Jan 2017 02:13

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