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Sub-100nm ferroelectric-gate thin film transistor fabricated by two-step patterning method

Hong Minh Do and Duc Thang Pham and Nguyen Quoc Trinh Bui (2016) Sub-100nm ferroelectric-gate thin film transistor fabricated by two-step patterning method. In: SW4PHD: the 2016 Scientific Workshop for PhD Students, 26 March 2016, Hanoi.

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Abstract

Ferroelectric-gate thin film transistor (FGT) which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator has attracted wide attention for the application of a new nonvolatile memory because of its prominent features such as simple device structure, high-speed operation and low power consumption. Recently, we have reported on demonstration of the of FGTs operation. However, the FGTs developed have channel lengths (LDS) more than 100 nm, which should be reduced for high-density storage in integration circuits.1-2) In this paper, we will present a new method to fabricate the sub-100 nm FGT, of which the source-drain gap would be surely created, in principle, comparing with the conventional patterning method. Electrical properties and memory functionalities of the fabricated sub-100nm FGTs will be investigated and discussed in detail.

Item Type:Conference or Workshop Item (Poster)
Subjects:Engineering Physics
Divisions:Faculty of Engineering Physics and Nanotechnology (FEPN)
ID Code:1565
Deposited By: Dr Ngoc Thang Bui
Deposited On:23 May 2016 02:17
Last Modified:23 May 2016 02:19

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