VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2024-03-29T13:20:21ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2017-06-10T11:54:35Z2017-12-07T06:51:13Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2490This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/24902017-06-10T11:54:35ZAES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing applicationsConnected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as Advanced Encryption Standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for Advanced Encryption Standard (AES) for high speed, ultra-low power, ultra-low energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and
key expansion. The estimated power results show that our
implementation may achieve an energy per bit comparable with
the lightweight standardized algorithm PRESENT of less than
1pJ/bit at 10MHz at 0.6V with throughput of 28Mbps in ST
FDSOI 28nm technology. In terms of security evaluation, our
proposed datapath, 32-bit key out of 128 bits cannot be revealed by Correlation Power Analysis (CPA) attack using less than 20 thousand traces.Duy Hieu Buihieubd@vnu.edu.vnDiego Puschinidiego.puschini@cea.frSimone Bacles-MinSimone.BACLES-MIN@cea.frEdith Beigneedith.beigne@cea.frXuan Tu Trantutx@vnu.edu.vn2016-05-14T14:44:46Z2017-01-17T02:20:44Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1511This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/15112016-05-14T14:44:46ZUltra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT ApplicationsIn this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.Duy Hieu Buihieubd@vnu.edu.vnDiego Puschinidiego.puschini@cea.frSimone Bacles-MinSimone.BACLES-MIN@cea.frEdith BeigneXuan Tu Trantutx@vnu.edu.vn