VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2022-01-19T02:26:53ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2020-12-13T16:04:40Z2020-12-13T16:04:40Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/4262This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/42622020-12-13T16:04:40ZThiết kế bộ khuếch đại công suất cao tần hiệu suất cao trên công nghệ CMOS 65nm cho các ứng dụng IoT tốc độ caoDuc Manh Tranducmanh.m18@gmail.comDuy Hieu Buihieubd@vnu.edu.vnThi Thuy Quynh Tranquynhttt@vnu.edu.vnVan Thanh Vu Levulvt@husc.edu.vnXuan Tu Trantutx@vnu.edu.vn2020-12-11T03:21:42Z2020-12-11T03:21:42Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/4242This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/42422020-12-11T03:21:42ZA Lightweight AEAD encryption core to secure IoT applicationsThe Internet of Things (IoT) with the advancements of many technologies opens a wide range of new applications such as smart appliances, smart cities and smart grids. Despite its popularity and usability, it also creates a new attack surface for the hackers especially on highly constrained devices which have limited memory footprints and processing power. These constrained devices often use Authenticated Encryption with Associated Data (AEAD) to secure data stored in the devices and transmitted over the network. In this work, we design a lightweight data encryption core in hardware with the support for AEAD to secure IoT applications on highly constrained devices. The design achieves a low area cost with only 23kGEs in TSMC 65nm technology and an encryption throughput of 123Mbps at 60MHz.Ngo Doanh Nguyendoanh.nn.97@gmail.comDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2020-10-29T07:03:43Z2020-10-29T07:03:43Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/4082This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/40822020-10-29T07:03:43ZLow Cost Inter-prediction Architecture in H.264/AVC Encoders with an Efficient Data Reuse StrategyAdvances in Engineering Research. Volume 40 first presents the characteristics of the laser-plasma extreme ultraviolet radiation from solid rare gas targets composed of Xe, Kr and Ar, along with the performances of the radiation sources developed using these targets.
Following this, the authors consider the most important issues related to creating a universal system of adaptive applications for use in the Internet of Things and Internet of People systems.
Previous techniques and recent advances in circuit techniques are reviewed, and a comparison of the reported techniques in the context of low-pass continuous-time Delta-Sigma modulators is presented.
A comprehensive overview of the properties of aggregates used on roads is provided, particularly focusing on their influence on the mechanical and skid resistance of road surfaces.
An analytical approach that allows for a rough prediction of the of the acoustic parameters of road surface is also presented. The attenuation depends on frequency, propagation distance, angle of incidence and geometric configuration of sources and sensors.
Due to computation complexity, the VLSI implementation of Inter-Prediction in the H.264/Advanced Video Coding imposes latency, memory bandwidth, and area cost challenges. To tackle these obstacles, the authors discuss a design methodology which exploits the relationship between the main processes in inter-prediction to enhance the performance while keeping an affordable design cost.
The penultimate study focuses on the way we can interpret linguistic algebra to understand and reverse translation formulas’ linguistic algebra into natural language text as a verbal expression of meaning. This will improve the performance of any computer system when working with text.
Recent computational tools of vector fields, including vector data representations, predictive models of spatial data, as well as applications in computer vision, signal processing and empirical sciences are reviewed in closing.Xuan Tu Trantutx@vnu.edu.vnNam Khanh Dangkhanh.n.dang@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnAlain Merigot2020-04-24T04:18:38Z2020-04-24T04:18:38Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3951This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/39512020-04-24T04:18:38ZAn Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC EncoderHEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.Dinh Lam Tranlamtdvdt@gmail.comXuan Tu TranDuy Hieu Buihieubd@vnu.edu.vnCong Kha Phampham@ee.uec.ac.jp2019-12-06T08:24:28Z2019-12-06T08:24:28Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3725This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/37252019-12-06T08:24:28ZAn Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural NetworksDeep Neural Networks (DNNs) have been successfully
applied to various real-world machine learning applications.
However, performing large DNN inference tasks in real-time
remains a challenge due to its substantial computational costs. Recently, Spiking Neural Networks (SNNs) have emerged as an alternative way of processing DNN’s task. Due to its eventbased, data-driven computation, SNN reduces both inference latency and complexity. With efficient conversion methods from traditional DNN, SNN exhibits similar accuracy, while leveraging many state-of-the-art network models and training methods. In this work, an efficient neuromorphic hardware architecture for image recognition task is presented. To preserve accuracy, the analog-to-spiking conversion algorithm is adopted. The system aims to minimize hardware area cost and power consumption, enabling neuromorphic hardware processing in edge devices. Simulation results have shown that, with the MNIST digit recognition task, the system has achieved ×20 reduction in terms
of core area cost compared to the state-of-the-art works, with an accuracy of 94.4%, core area of 15 μm2 at a maximum frequency of 250 MHz.Duy Anh Nguyendanguyen@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnFrancesca IacopiFrancesca.Iacopi@uts.edu.auXuan Tu Trantutx@vnu.edu.vn2019-12-06T07:55:14Z2020-07-14T09:40:56Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3721This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/37212019-12-06T07:55:14ZA Variable Precision Approach for Deep Neural NetworksDeep Neural Network (DNN) architectures have been recently considered as the big breakthrough for a variety of applications. Because of the high computing capabilities required, DNN has been unsuitable for various embedded applications. Many works have been trying to optimize the key operations, which are multiply-and-add, in hardware for a smaller area, higher throughput, and lower power consumption. One way to optimize these factors is to use the reduced bit accuracy; for examples, Google's TPU used only 8-bit integer operations for DNN inference. Based on the characteristics of different layers in DNN, further bit accuracy can be changed to preserve the hardware area, power consumption, and throughput. In this work, the thesis investigates a hardware implementation of multiply-and-add with variable bit precision which can be adjusted at the computation time. The proposed design can calculate the sum of several products with the bit precision ranging from 1 to 16 bits. The hardware implementation results on Xilinx FPGA Virtex 707 development kit show that our design occupies smaller hardware and can run at a higher frequency of 310 MHz, while the same functionality implemented with and without DSP48 blocks can only run at a frequency of 102 MHz. In addition, to demonstrate that the proposed design is applicable effectively for deep neural network architecture, the paper also integrated the new design in the MNIST network. The simulation and verification results show that the proposed system can achieve the accuracy up of to 88%.Xuan Tuyen Tranxuantuyen2901@gmail.comDuy Anh Nguyendanguyen@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2019-12-06T07:47:53Z2019-12-06T07:47:53Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3722This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/37222019-12-06T07:47:53ZA Dual Polarization SIW Slot Antenna Adopting TM340 And TM430 Modes in the X-bandThis paper presents a dual polarization SIW slot antenna with high order TM430 and TM340 modes. The antenna consists of a radiation resonant SIW layer and two feeding network layers. Through detailed analysis, the TM430 and TM340 modes are used to design two different polarized waves. Moreover, a SIW dual polarization slot array antenna with three substrate layers is designed and fabricated. The measured impedance bandwidth (S11 < -10 dB) of the array antenna is from 10.75 to 10.83 GHz for the dual polarization, and the measured maximum gains are 13.4 and 12.92 dBi, respectively.Wenxun LiXiaohong TangYang YangYang.Yang-1@uts.edu.auXuan Tu Trantutx@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vn2019-12-06T07:41:03Z2019-12-06T07:41:03Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3723This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/37232019-12-06T07:41:03ZA Novel Hardware Architecture for Human Detection using HOG-SVM Co-OptimizationHistogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 110kb SRAMs.Ngo Doanh Nguyendoanh.nn.97@gmail.comDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2019-07-05T04:39:33Z2020-01-04T15:07:35Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3545This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/35452019-07-05T04:39:33ZQuy trình mã hóa liên khung hình hỗ trợ xác định khối ảnh lặp lại, giảm kích thước chuỗi bit sau mã hóa và loại bỏ hiệu ứng do sai số lượng tử cho khối ảnh lặp lạiSáng chế đề cập đến quy trình mã hóa liên khung hình (inter-frame coding) cho phép xác định các khối ảnh lặp lại. Sau đó, thực hiện một quy trình mã hóa riêng cho các khối ảnh lặp lại nhằm giảm kích thước chuỗi bit mã hóa và loại bỏ các ảnh hưởng tiêu cực của sai số lượng tử. Bên cạnh đó, sáng chế cũng trình bày một số giải pháp để tăng tốc công đoạn xác định khối ảnh lặp lại.Xuan Tu Trantutx@vnu.edu.vnNgoc Sinh Nguyensinhnn_55@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vn2018-10-10T01:32:35Z2018-12-22T02:40:45Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3114This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/31142018-10-10T01:32:35ZAn Efficient Hardware Implementation of Artificial Neural Network based on Stochastic ComputingDuy Anh Nguyendanguyen@vnu.edu.vnHuy Hung Hohhhung96@gmail.comDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2018-10-10T01:28:15Z2020-02-03T06:56:58Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3113This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/31132018-10-10T01:28:15ZReducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Error in Stationary BlocksIn image compression and video coding, quantization error helps to reduce the amount of information of the high frequency components. However, in temporal prediction the quantization error contributes its value as noise in the total residual information. Therefore, the residual signal of the inter-picture prediction is greater than the expected one and always differs zero value even input video contains only homogeneous frames. In this paper, we reveal negative effects of quantization errors in inter prediction and propose a video encoding scheme which is able to avoid side effects of quantization errors in the stationary parts. We propose to implement a motion detection algorithm as the first stage of video encoding to separate the video into two parts: motion and static. The motion information allows us to force residual data of non-changed part to zero and keep the residual signal of motion regularly. Beside, we design block-based filters which improve motion results and filter those results fit into block encode size well. Fixed residual data of static information permits us to pre-calculate its quantized coefficient and create a bypass encoding path for it. Experimental results with the JPEG compression (MJPEG-DPCM) showed that the proposed method produces lower bitrate than the conventional MJPEG-DPCM at the same quantization parameter and a lower computational complexity.Xuan Tu Trantutx@vnu.edu.vnNgoc Sinh Nguyensinhnn_55@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnKiem Hung Nguyenkiemhung@vnu.edu.vnMinh Trien Phamtrienpm@vnu.edu.vnCong Kha Phampham@ee.uec.ac.jp2018-06-14T07:04:02Z2018-06-14T07:04:02Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2967This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/29672018-06-14T07:04:02ZAdaptive Architectures, Circuits and Technology Solutions for Future IoT SystemsConsidering different sources of variations encountered by integrated circuits and systems today, adaptivity is a key challenge for designers. More specifically, this paper will propose different techniques, in the IoT domain, to cope with process-voltage-temperature variations as well as applicative and environmental variations. An overview of different techniques is given in the paper to be applied on gateways and also on IoT sensor nodes. Techniques like Adaptive Voltage and Frequency Scaling, adaptive imagers, wake-up radios or flexible security will be discussed. In any case, global power management is discussed in order to reach high energy efficiency and minimum energy losses while considering changing power supply environment.Marc BellevilleAnca MolnosGilles SicardJean Frederic ChristmannDominique MorcheDuy Hieu Buihieubd@vnu.edu.vnDiego Puschinidiego.puschini@cea.frSuzanne LesecqEdith Beigneedith.beigne@cea.fr2017-12-08T07:21:37Z2017-12-08T07:21:37Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2746This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/27462017-12-08T07:21:37ZAccurate and Low Complex Cell Histogram Generation by Bypass the Gradient of Pixel ComputationHistogram of Oriented Gradient (HOG) is a popular
feature description for the purpose of object detection. However, HOG algorithm requires a performance system because of its complex operation set. Especially, the cell histogram generation is one of the most complex part, it uses inverse tangent, square, square root, floating point multiplication. In this paper, we propose an accurate and low complex cell histogram generation by bypass the gradient of pixel computation. It employs the bin’s
boundary angle method to determine the two quantized angles. However, instead of choosing an approximate value of tan, the nearest greater and the nearest smaller of each tan values from ratio between pixel’s derivative in y and x direction are used. Magnitude of two bins are solutions of a system of two equations, which represent the equality of the gradient of a pixel and its two bins in both vertical and horizontal direction. The proposed
method spends only 30 addition and 40 shift operations to identify two bins of a pixel. Simulation results show that the percentage error when reconstructing the difference in x and y direction are always less than 2% with 8-bit length of the fractional part. Additionally, manipulating the precision of gradient magnitude is very simple by pre-defined sine and cosine values of quantized angles. Synthesizing the hardware implementation presents that
its area cost is 3.57 KGates with 45nm NanGate standard cell library. The hardware module runs at the maximum frequency of 400 MHz, and the throughput is 0.4 (pixel/ns) for a single module. It is able to support about 48 fps with 4K UHD resolution.Huy Hung Hohhhung96@gmail.comNgoc Sinh Nguyensinhnn_55@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2017-12-08T03:27:18Z2017-12-08T03:27:18Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2745This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/27452017-12-08T03:27:18ZEfficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin ProcessingThe increasing amount of digital video with supreme quality requires more efficient compression. As the complexity of video coding algorithm is rising, there are more demands for hardware accelerators and customized hardware. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coding method adopted in the latest video compression standard, High Efficiency Video Coding (HEVC). Binary Arithmetic Encoder (BAE) is an essential component in CABAC, where the compression process happens. Because of the high data dependency and sequential coding characteristic, it is challenging to parallelize BAE. In this work, we proposed a low-cost and high-throughput hardware architecture for one core of BAE in HEVC. Our 4-stage pipelined BAE architecture is capable of processing one regular bin and up to 4 bypass bins per clock cycle with 30% reduction in terms of area when compared with the designs for one-core CABAC architecture. The design can compress an average of 1.4 bins per cycle. It achieves a throughput of 1 Gbin/s at the maximum operating frequency of 810 MHz with the area of 2.2 kGEs and the power consumption of 2.0 mW in Nangate 45nm technology.Quang Linh Nguyennqlinh.95@gmail.comDinh Lam Tranlamtdvdt@gmail.comDuy Hieu Buihieubd@vnu.edu.vnDuc Tho Maimaiductho071@gmail.comXuan Tu Trantutx@vnu.edu.vn2017-06-10T11:54:35Z2017-12-07T06:51:13Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2490This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/24902017-06-10T11:54:35ZAES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing applicationsConnected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as Advanced Encryption Standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for Advanced Encryption Standard (AES) for high speed, ultra-low power, ultra-low energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and
key expansion. The estimated power results show that our
implementation may achieve an energy per bit comparable with
the lightweight standardized algorithm PRESENT of less than
1pJ/bit at 10MHz at 0.6V with throughput of 28Mbps in ST
FDSOI 28nm technology. In terms of security evaluation, our
proposed datapath, 32-bit key out of 128 bits cannot be revealed by Correlation Power Analysis (CPA) attack using less than 20 thousand traces.Duy Hieu Buihieubd@vnu.edu.vnDiego Puschinidiego.puschini@cea.frSimone Bacles-MinSimone.BACLES-MIN@cea.frEdith Beigneedith.beigne@cea.frXuan Tu Trantutx@vnu.edu.vn2017-06-03T10:07:05Z2017-08-08T14:50:22Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2468This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/24682017-06-03T10:07:05ZAXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip ArchitecturesThe increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793um2 with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.Xuan Tu Trantutx@vnu.edu.vnTung NguyenHai Phong Phanhaiphongphan@gmail.comDuy Hieu Buihieubd@vnu.edu.vn2016-05-14T14:44:46Z2017-01-17T02:20:44Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1511This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/15112016-05-14T14:44:46ZUltra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT ApplicationsIn this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.Duy Hieu Buihieubd@vnu.edu.vnDiego Puschinidiego.puschini@cea.frSimone Bacles-MinSimone.BACLES-MIN@cea.frEdith BeigneXuan Tu Trantutx@vnu.edu.vn2014-12-31T07:58:33Z2017-01-17T02:25:56Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/436This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4362014-12-31T07:58:33ZXây dựng hệ thống mô phỏng và kiểm chứng cho bộ mã hoá tín hiệu video H.264/AVCSự phức tạp của hệ thống mã hoá tín hiệu video H.264/AVC đã dẫn tới nhiều khó khăn trong việc kiểm tra, kiểm chứng và kiểm thực các thiết kế ở mức hệ thống của bộ mã hoá này. Những khó khăn chúng tôi gặp phải khi thiết kế và thực thi hệ thống này là việc quản lý các kịch bản kiểm tra; thay đổi các tham số của hệ thống và của kịch bản kiểm tra; và thời gian chạy mô phỏng lâu đối với các tập dữ liệu dùng để kiểm tra và kiểm chứng hệ thống, đặc biệt là khi hệ thống được ghép nối với một hệ thống trên chip (System-on-chip). Trong báo cáo này, chúng tôi trình bày một phương pháp xây dựng hệ thống mô phỏng và kiểm chứng ở mức hệ thống bộ mã hoá tín hiệu video H.264/AVC dựa trên việc thiết kế kịch bản kiểm tra và kiểm chứng tối giản và linh động, kết hợp với các phần mềm mã nguồn mở sẵn có như GNU Make, ngôn ngữ Python để tạo thành một hệ thống kiểm tra và kiểm chứng tự động, cho phép tự động mô phỏng thiết kế từ mức hành xử cho đến mức cổng lô-gíc. Hệ thống này cho phép chạy nhiều mô phỏng tại cùng một thời điểm với các kịch bản kiểm tra khác nhau. Nhờ việc này, chúng tôi đã giảm được thời gian chạy mô phỏng từ 2 đến 10 lần phụ thuộc vào khả năng của máy chạy mô phỏng. Kịch bản kiểm tra được thực hiện trên VHDL để kiểm tra thiết kế của bộ mã hoá tín hiệu video H.264/AVC thực thi trên công nghệ 130nm của hãng Global Foundry.Duy Hieu Buihieubd@vnu.edu.vnNam Khanh Dangdnk0904@gmail.comNgoc Mai Nguyenmainn@vnu.edu.vnKiem Hung Nguyenkiemhung@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2014-12-31T05:29:04Z2017-01-17T02:24:18Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/431This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4312014-12-31T05:29:04ZA Low-Cost Implementation of Advance Encryption StandardThe fast development of the Internet enables the information to be easily shared on a global network, however, it also raises the concerns about the secure of the information especially the sensitive data such as passwords, bank accounts, personal information and so on. One method to protect the sensitive data is using symmetric-key block cypher before and after sending
it over the network using same secret key. Advanced Encryption Standard (AES) is currently considered as best symmetric-key block cipher. With the block size of 128-bits and the key length starting from 128-bit up to 256-bits, AES has been proved to takes years to break. However, AES implementations in software also require more computations and time to encrypt and decrypt the data. This bottleneck not only reduces the overall system throughput but also increases the power consumption especially in the embedded system, where there are limited computations and resources. To improve the throughput and reduce the power consumption of the AES crypto system, in this work, we proposed a combined, low-cost and high-throughput AES encryption and decryption architecture supporting all key-lengths as specified in the FIPS197. The design was modeled in VHDL and
successfully synthesized using Xilinx Virtex 5 FPGA Chip 5VSX50TF with maximum frequency of 105 MHz and the maximum
throughput of 300 Mbps.Tien Luan Vuluanvt_56@vnu.edu.vnVan Quy Quachquyqv_56@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2014-12-31T05:14:44Z2017-01-17T02:22:58Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/430This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4302014-12-31T05:14:44ZH.264/AVC Hardware Encoders and Low-Power FeaturesBecause of significant bit rate reduction in comparison to the previous video compression standards, the H.264/AVC has been successfully used in a wide range of applications. In hardware design for H.264/AVC video encoders, power reduction is currently a tremendous challenge. This paper presents a survey of different H.264/AVC hardware encoders focusing on power features and power reduction techniques to be applied. A new H.264/AVC hardware encoder, named VENGME, is proposed. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at RTL level, is 19.1mW.Ngoc-Mai Nguyenmainn@vnu.edu.vnEdith BeigneSuzanne LesecqDuy Hieu Buihieubd@vnu.edu.vnNam Khanh DangXuan Tu Trantutx@vnu.edu.vn2014-12-29T04:17:52Z2017-01-17T02:23:20Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/426This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4262014-12-29T04:17:52ZReducing Temporal Redundancy in MJPEG using Zipfian Estimation TechniquesThe bit-rate is the one the most crucial factor in storing and transmitting the digital videos while the complexity plays the most important part in embedded systems.Nowadays, H.264/AVC and newest video advance codec are great in reducing bit-rate. However, these codec have high processing dependencies and complexity. This leads to difficulties in implementing them into the embedded systems, maintaining the real time properties of the system and power consumption problems. Therefore, MJPEG standard is still widely used in the embedded systems even it is inefficient in reducing the bit-rate. In this paper, we improve the quality and the bitrate of the MJPEG codec with low-complexity techniques: temporal compression and encoding residual values in motions.
Motion JPEG simply compresses each frame in a video sequence using JPEG still image compression standard. This video codec satisfies power consumption and real-time properties of embedded systems while having very low complexity. However, the downside is its inefficiency in reducing the bit-rate because there are still redundancies between encoded frames. In this paper, we focus on reducing temporal redundancies in MJPEG using a motion detection algorithm, called Zipfian estimation. The Zipfian estimation helps MJPEG extract separately the moving blocks and the stationary blocks then removes temporal redundancies by minimizing encoded bit-stream of stationary blocks and encoding only the residuals of the moving blocks between adjacent frames. Experimental results show that the proposed method can provide twice compression ratio as much as the conventional MJPEG, and an approximate quality and bit-rate as the H.264/AVC (Intra-mode). Even the proposed method uses the Zipfian estimation, it still has smaller number of operations than the conventional MJPEG if the percentage of the static scene is equal or greater than 60%. Compared with the H.264/AVC Intra mode when turning off the rate-distortion optimization, the running time of the proposed method is still only a half.Ngoc Sinh Nguyensinhnn_55@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2014-12-27T11:42:47Z2017-01-17T02:14:55Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/425This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4252014-12-27T11:42:47ZAn Overview of H.264 Hardware Encoder Architectures including Low-Power FeaturesH.264 is the most popular video coding standard with high potent coding performance. For its efficiency, the H.264 is expected to encode real-time and/or high-definition video. However, the H.264 standard also requires highly complex and long lasting computation. To overcome these difficulties, many efforts have been deployed to increase encoding speed. Besides, with the revolution of portable devices, multimedia chips for mobile environments are more and more developed. Thus, power-oriented design for H.264 video encoders is currently a tremendous challenge. This paper discusses these trends and presents an overview of the state of the art on power features for different H.264 hardware encoding architectures. We also propose the VENGME's design, a particular hardware architecture of H.264 encoder that enables applying low-power techniques and developing power-aware ability. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at Register-Transfer-Level (RTL), is only 19.1mW.Ngoc Mai Nguyenmainn@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnNam Khanh Dangdnk0904@gmail.comEdith BeigneSuzanne LesecqPascal Vivetpascal.vivet@cea.frXuan Tu Trantutx@vnu.edu.vn2013-12-12T09:22:53Z2017-01-17T02:29:53Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/417This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4172013-12-12T09:22:53ZSystem-on-Chip Testbed for Validating the Hardware Design of H.264/AVC EncoderThis paper presents an implementation of a LEON3-based System-on-Chip (SoC) testbed, which is aimed at experimentally evaluating and validating the H.264/AVC video encoding Integrated Circuit (IC) developed by SIS Laboratory at VNU University of Engineering and Technology. In addition, the paper also presents a methodology for verifying the design of H264/AVC video encoder in the Hardware/Software co-emulating fashion. The design is implemented on the DE2 development board from Altera Corporation. The testbed can help us to evaluate effectively many aspects of the developed H.264/AVC video encoder.Hai Phong Phanhaiphongphan@gmail.comKiem Hung Nguyenkiemhung@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnNam Khanh Dangdnk0904@gmail.comXuan Tu Trantutx@vnu.edu.vn2013-07-17T04:35:34Z2017-01-17T02:30:48Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/169This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/1692013-07-17T04:35:34ZHigh-Performance Adaption of ARM Processor into Network-on-Chip ArchitecturesThe demand for system scalability, reusability, and the decoupling between computation and communication have motivated the growth of Network-on-Chip (NoC) paradigm in the recent years. The system design has changed from the computation centric design to the communication centric design. Researchers have proposed a number of NoC architectures. Most of these works focus on network architectures and routing algorithms, however, the interfaces between network architectures and processing units also need to be addressed to improve the overall performance of the system. This paper presents an efficient AXI (Advanced eXtensible Interface) compliant network adapter for 2D mesh Wormhole-based NoC architectures, named AXI-NoC adapter. The proposed network adapter achieves high frequency of 650MHz with a low area footprint (952 cells, approximate to 2,793um2 with a CMOS 45nm technology) by using an effective micro-architecture and with zero latency by using the mux-selection method.Tung NguyenDuy Hieu Buihieubd@vnu.edu.vnHai Phong Phanhaiphongphan@gmail.comTrong Trinh DangXuan Tu Trantutx@vnu.edu.vn2012-11-02T06:06:39Z2017-01-17T02:36:06Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/47This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/472012-11-02T06:06:39ZMulti-level Design Methodology using SystemC and VHDL for JPEG EncoderNowadays, System-on-Chip (SoC) systems are becoming more and more complex and need more time to model, simulate and verification. To reduce the complexity of the system and to boost development time, a new design methodology is required. Along with SystemC library, multi-level abstraction design methodology is proposed as the key concept in SoC design. In this paper, the authors apply this methodology to model and simulate a JPEG encoder using the combination of SystemC and VHDL to explore the architecture and implement the design into hardware components. Consequently, some parts of the JPEG encoder has successfully synthesized and implemented using FPGA tools. In conclusion, the design methodology gives designers a fast way and step-by-step to explore the hardware architecture, simulate and implement the system.Duy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2012-11-02T02:28:57Z2017-01-17T02:34:39Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/41This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/412012-11-02T02:28:57ZA Hardware Architecture for Intra Prediction in H.264/AVC EncoderMPEG-4 AVC, so called H.264/AVC, is the latest video compression standard focusing on network transport and
storage of digital multimedia. In H.264 system, the intra prediction module is one of the most essential parts and it is different from the previous video compression standards. With the new prediction techniques, intra prediction in H.264 improves the bit rate but it also increases the memory bandwidth and the computational complexity with many prediction modes. In this work, the intra prediction procedure is fully analyzed. Based on the analysis, a hardware architecture for intra prediction focused on
main profile of H.264/AVC is proposed. The proposed architecture uses an adder tree to generate the predicted pixels for all prediction modes. The cost calculation method is Sum of Absolute Transformed Difference (SATD) and mode decision is the full search scheme. The proposed architecture can do intra prediction of an HDTV input in real-time and it is successfully simulated using Modelsim and synthesized using Xilinx ISE 10.1.Duy Hieu Buihieubd@vnu.edu.vnVan Huan Tranhuantv@vnu.edu.vnVan Mien Nguyenmiennv@vnu.edu.vnDuc Hoang NgoXuan Tu Trantutx@vnu.edu.vn