VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2024-03-29T12:54:11ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2020-10-13T08:45:45Z2020-10-13T08:45:45Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/4081This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/40812020-10-13T08:45:45ZLow-power High-performance 32-bit RISC-V Microcontroller on 65-nm Silicon-On-Thin-BOX (SOTB)In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (VDD) with +1.6-V back-gate bias voltage (VBB). The best power density of 33.4-µW/MHz is reached at 0.5-V VDD with +0.8-V VBB. The least current leakage of 3-nA is retrieved at 0.5-V VDD with -2.0-V VBB.Trong Thuc HoangCkristian DuranKhai Duy NguyenTuan Kiet DangQuang Nhu Quynh NguyenPhuc Hong ThanXuan Tu Trantutx@vnu.edu.vnDuc Hung LeAkira TsukamotoKuniyasu SuzakiCong Kha Phampham@ee.uec.ac.jp2020-04-24T04:18:38Z2020-04-24T04:18:38Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3951This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/39512020-04-24T04:18:38ZAn Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC EncoderHEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.Dinh Lam Tranlamtdvdt@gmail.comXuan Tu TranDuy Hieu Buihieubd@vnu.edu.vnCong Kha Phampham@ee.uec.ac.jp2018-10-10T01:28:15Z2020-02-03T06:56:58Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/3113This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/31132018-10-10T01:28:15ZReducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Error in Stationary BlocksIn image compression and video coding, quantization error helps to reduce the amount of information of the high frequency components. However, in temporal prediction the quantization error contributes its value as noise in the total residual information. Therefore, the residual signal of the inter-picture prediction is greater than the expected one and always differs zero value even input video contains only homogeneous frames. In this paper, we reveal negative effects of quantization errors in inter prediction and propose a video encoding scheme which is able to avoid side effects of quantization errors in the stationary parts. We propose to implement a motion detection algorithm as the first stage of video encoding to separate the video into two parts: motion and static. The motion information allows us to force residual data of non-changed part to zero and keep the residual signal of motion regularly. Beside, we design block-based filters which improve motion results and filter those results fit into block encode size well. Fixed residual data of static information permits us to pre-calculate its quantized coefficient and create a bypass encoding path for it. Experimental results with the JPEG compression (MJPEG-DPCM) showed that the proposed method produces lower bitrate than the conventional MJPEG-DPCM at the same quantization parameter and a lower computational complexity.Xuan Tu Trantutx@vnu.edu.vnNgoc Sinh Nguyensinhnn_55@vnu.edu.vnDuy Hieu Buihieubd@vnu.edu.vnKiem Hung Nguyenkiemhung@vnu.edu.vnMinh Trien Phamtrienpm@vnu.edu.vnCong Kha Phampham@ee.uec.ac.jp