VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2024-03-28T09:25:09ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2017-11-08T07:18:14Z2017-11-08T07:18:14Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2621This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/26212017-11-08T07:18:14ZInterface Charge Trap Density of Solution Processed Ferroelectric Gate Thin Film Transistor Using ITO/PZT/Pt StructureThe conductance method was applied to investigate the interface charge trap density
(Dit) of solution processed ferroelectric gate thin film transistor (FGT) using indium-tin
oxide (ITO)/ Pb(Zr,Ti)O3 (PZT)/Pt structure. As a result, a large value of Dit of MFS
capacitor, i.e., Pt/PZT/ITO, was estimated to be 1.2 × 1014 eV−1 cm−2. This large Dit
means that an interface between the ITO layer and the PZT layer is imperfect and it is
one of themain reasons for the poor memory property of this FGT. By using transmission
electron microscopy (TEM), this imperfect interface was clearly observed. Thus, it is
concluded that improvement of this interface is critical for better memory performance.Van Thanh PhamNguyen Quoc Trinh Buitrinhbnq@vnu.edu.vnMiyasako TakaakiTrong Tue PhanTokumitsu EisukeShimoda Tatsuya2017-11-08T07:13:14Z2017-11-08T07:13:14Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2619This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/26192017-11-08T07:13:14ZElectric Properties and Interface Charge Trap Density of Ferroelectric Gate Thin Film Transistor Using (Bi,La)4Ti3O12/Pb(Zr,Ti)O3 Stacked Gate InsulatorWe successfully fabricated ferroelectric gate thin film transistors (FGTs) using solution-processed (Bi,La)4Ti3O12 (BLT)/Pb(Zr,Ti)O3 (PZT)
stacked films and an indium–tin oxide (ITO) film as ferroelectric gate insulators and an oxide channel, respectively. The typical n-type channel
transistors were obtained with the counterclockwise hysteresis loop due to the ferroelectric property of the BLT/PZT stacked gate insulators.
These FGTs exhibited good device performance characteristics, such as a high ON/OFF ratio of 106, a large memory window of 1.7–3.1 V, and a
large ON current of 0.5–2.5 mA. In order to investigate interface charge trapping for these devices, we applied the conductance method to MFS
capacitors, i.e., Pt/ITO/BLT/PZT/Pt capacitors. As a result, the interface charge trap density (Dit) between the ITO and BLT/PZT stacked films
was estimated to be in the range of 10�11–10�12 eV�1 cm�2. The small Dit value suggested that good interfaces were achieved.Van Thanh PhamNguyen Quoc Trinh Buitrinhbnq@vnu.edu.vnMiyasako TakaakiTrong Tue PhanTokumitsu EisukeShimoda Tatsuya