VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2024-03-28T09:32:49ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2017-04-12T01:56:14Z2017-04-12T01:56:14Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2457This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/24572017-04-12T01:56:14ZPower Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-ChipDynamic Voltage and Frequency Scaling (DVFS) has been known as an efficient technique to reduce the power consumption of a Network-on-Chip (NoC). An important question in DVFS is how to change the voltage and frequency adaptable to the required performance of the system at run-time while reducing the power consumption as much as possible. Another
problem is how a tool could quickly and efficiently validate
or reject a NoC architecture employing DVFS. By integrating
the Orion 2 power model, VNOC 2.0 simulator can be used as
either a NoC simulation tool or a platform for implementing and investigating DVFS ideas. In this paper, we focus on developing a new solution for NoC architectures to save energy using fuzzy-logic algorithms. A controller is designed to predict the change of traffic load based on the fuzzy logic algorithm, then adjusts the voltage and frequency correspondingly to minimize the power consumption while keeping the performance of the whole system. An estimation of power consumption has been done by using
VNOC 2.0 simulator. The simulation results show that our model can save up to 46% the power consumption of a 8x8 NoC.Hai Phong Phanhaiphongphan@gmail.comXuan Tu Trantutx@vnu.edu.vnTomohiro Yonedayoneda@nii.ac.jp