VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2024-03-28T15:26:41ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2012-11-02T06:24:48Z2017-01-17T02:36:40Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/51This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/512012-11-02T06:24:48ZCost-Efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC EncodersIn this paper, we present a low cost Forward Transform and Quantization (FTQ) implementation for H.264/AVC encoders in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast
architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755um2 (approximate 15KGates), with the 130nm TSMC CMOS technology.Xuan Tu Trantutx@vnu.edu.vnVan Huan Tranhuantv@vnu.edu.vn2012-11-02T06:19:52Z2017-01-17T02:37:01Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/50This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/502012-11-02T06:19:52ZAn Efficient Architecture Design for VGA Monitor ControllerIn this paper, we present the design and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The design is compatible with PLB bus and has a high potential to be used in Xilinx FPGA-based systems. The ability to provide multiple display resolutions (up to WXGA 1280x800) and a customizable internal FIFO make the proposed architecture suitable for several FPGA devices. Furthermore, we have also offered a useful software library to enable the text mode feature. These highlight features have been validated through the demonstration of an application.Van Huan Tranhuantv@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2012-11-02T06:14:37Z2017-01-17T02:36:21Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/49This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/492012-11-02T06:14:37ZNetwork-on-Chips: Design and Test Challenges in Nanoscale EraNowadays, more and more complex intellectual property (IP) cores communicating with each other has been intently integrated into a system to meet the high demand of new applications. This make the on-chip communication become a critical issue and the conventional bus based communication using a single bus or a hierarchy of busses could not response to the communication requirements between the integrated IP cores because of their poor scalability with system size, their shared bandwidth between all the integrated IPs, and the energy efficiency requirements of final products.
To overcome those problems, the Network-on-Chip (NoC) paradigm has been proposed as a promising on-chip communication solution for designing complex systems, especially when the semiconductor technology turns into nanoscale era. However, the development of design and test methodologies for this new paradigm is a complicated and time consuming engineering process, concerning to not only hardware design issues but also network protocols matters. After a decade of research and development, the NoC designers still have to face many challenges to bring the paradigm to final industrial products.
This talk will first give a brief introduction to the network-on-chip concept, and then addresses on main challenges in de-signing and testing the on-chip communication network well as the attached IP cores. A practical example of designing and testing a network on chip will be also presented to illustrate the mentioned challenges.Xuan Tu Trantutx@vnu.edu.vn2012-11-02T06:10:35Z2017-01-17T02:35:45Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/48This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/482012-11-02T06:10:35ZFPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router ArchitectureThe Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows.Nam Khanh Dangdnk0904@gmail.comVan Thanh Vu Levulvt@husc.edu.vnXuan Tu Trantutx@vnu.edu.vn2012-11-02T06:06:39Z2017-01-17T02:36:06Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/47This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/472012-11-02T06:06:39ZMulti-level Design Methodology using SystemC and VHDL for JPEG EncoderNowadays, System-on-Chip (SoC) systems are becoming more and more complex and need more time to model, simulate and verification. To reduce the complexity of the system and to boost development time, a new design methodology is required. Along with SystemC library, multi-level abstraction design methodology is proposed as the key concept in SoC design. In this paper, the authors apply this methodology to model and simulate a JPEG encoder using the combination of SystemC and VHDL to explore the architecture and implement the design into hardware components. Consequently, some parts of the JPEG encoder has successfully synthesized and implemented using FPGA tools. In conclusion, the design methodology gives designers a fast way and step-by-step to explore the hardware architecture, simulate and implement the system.Duy Hieu Buihieubd@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2012-11-02T03:56:38Z2017-01-17T02:15:16Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/45This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/452012-11-02T03:56:38ZCoMoSy: a Flexible System-on-Chip Platform for Embedded ApplicationsThanks to the rapid evolution of semiconductor
technology, System-on-Chip (SoC) paradigm has become
one of the most common design methodologies for
quickly developing embedded systems to meet the high
demands of embedded applications. In this paper, we
present the design and implementation of a SoC platform
targeted to controlling and monitoring applications. This
proposed platform is composed of a 32-bit processor and
a dozen of common hardware interfaces, providing the
programmability and connectivity to peripheral devices
such as memories, LAN network, monitor, keyboard, ADC,
DAC, or other I/O devices. In addition, to increase the
flexibility of the system and to rapidly develop end-user
applications, we also deploy an application-specific
software framework with the robustness of a lightweight
kernel and real-time applet management. The system
model has finally been validated through the realization
of a remote control camera system.Van Huan Tranhuantv@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2012-02-20T05:07:21Z2017-01-17T02:15:45Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/30This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/302012-02-20T05:07:21ZAn Efficient Architecture of Forward Transforms and Quantization for H.264/AVC CodecsThanks to many novel coding tools, H.264/AVC has become the most efficient video compression standard providing much better performance than previous standards. However, this standard comes with an extraordinary computational complexity and a huge memory access requirement, which make the hardware architecture design much more difficult and costly, especially for real-time applications.
In the framework of H.264 codec hardware architecture project, this paper presents an efficient architecture of Forward Transform and Quantization (FTQ) for H.264/AVC codecs in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755um2 (approximate 15KGates), with the 130nm TSMC CMOS technology.Xuan Tu Trantutx@vnu.edu.vnVan Huan Tranhuantv@vnu.edu.vn