VNU-UET Repository: No conditions. Results ordered -Date Deposited. 2024-03-28T19:44:23ZEPrintshttp://eprints.uet.vnu.edu.vn/images/sitelogo.pnghttps://eprints.uet.vnu.edu.vn/eprints/2016-12-04T13:44:22Z2017-01-17T02:46:19Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/2062This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/20622016-12-04T13:44:22ZThe 2016 Annual Scientific Report of VNU University of Engineering and TechnologyThe University of Engineering and Technology (UET) was founded in 2004 as a member university of Vietnam National University, Hanoi (VNU).
The last only five years have seen immense progresses in the development of our university in various aspects of its activities thanks to the great efforts put in by the government with strong financial supports, by the VNU with steering leadership and administration, by the national and international educational institutions and corporations in fruitful collaborations and advices, and by all the staff and students of the UET with determination, hard work and patience.
Today, our university has built up a solid foundation for a sustainable and dynamic development in coming years. This solid foundation consists of a completed system of well-designed programs at both undergraduate and graduate levels, renovated teaching and learning facilities, a just limited but strong and advanced research infrastructure with state-of-the-art and completed equipment systems, a sustainable and fruitful collaboration with leading research and educational institutions in the country, and a bright, young, well-educated and welltrained faculty who are eager to take on advanced research and studies. All these have made our university a prestigious institution and firmly established its education and research capabilities. This is proved by the facts that only in the last four years our university has established close and solid ties and cooperation with prestigious foreign universities, just to name a few, the University Paris-Sud 11 (France), Japan Advanced Institute of Science and Technology, the National University of Singapore, Nanyang Technological University (Singapore), University of New South Wales and with famous international industrial and technological corporations such as Samsung, Toshiba, NEC, Mitani, Human Resocia, IBM, and other well-known institutions in the region and around the world. This is also proved in a convincing way by the facts that only in the last two years, our university has been granted several significant research projects from various national research programs. Our university has become an attractive destination for talented students at all training levels. We are proud that our university is the only Vietnamese higher-education institution that has one among the 100 best student’s teams all over the world participating the World Final of the ACM International Collegiate Programming Contest (rank #29 in 2015). We are also proud that in this year, our faculty has won an award in the National Contest in Information Technology entitled “Vietnamese Talent Award” and three awards in the VNU Science & Technology Award for the period of 2011-2015. In the coming period, we shall put our great efforts to solidify our strength and prestige. We shall widen our training scope while paying significant attention to further improvement on the education quality. We shall strongly enhance our concentrated research activity by exploring efficiently and effectively our well established foundation for a further dynamic development and, thus, contributing our crucial part to the socio-economic development of our nation and fulfilling our great missions clearly assigned by the government in the decision on the establishment of our university. To do that, innovative thinking and acting by all faculty, administrative staff and students are of deciding role and of crucial importance.Xuan Tu Trantutx@vnu.edu.vnAnh Cuong Lecuongla@vnu.edu.vnDuc Tan Trantantd@vnu.edu.vnManh Thang Phamthangpm@vnu.edu.vnThi Huong Giang Dogiangdth@vnu.edu.vn2016-09-02T16:16:27Z2017-01-17T02:18:49Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1873This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/18732016-09-02T16:16:27ZDesign and Implementation of a Hybrid Switching Router for the Reconfigurable Network-on-ChipKiem Hung Nguyenkiemhung@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2016-09-02T16:13:11Z2017-01-17T02:19:31Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1872This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/18722016-09-02T16:13:11ZFuzzy-Logic based Low Power Solution for Network-on-Chip ArchitecturesHai Phong Phanhaiphongphan@gmail.comXuan Tu Trantutx@vnu.edu.vn2016-05-23T02:38:08Z2017-01-17T02:21:27Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1558This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/15582016-05-23T02:38:08ZKiến trúc mới cho giải pháp tái cấu hình mạng trên chipTrong báo cáo này chúng tôi giới thiệu một kiến trúc mới cho bộ định tuyến của mạng trên chip để thực hiện giải pháp tái cấu hình mạng trên chip (RNoC: Network-on-Chip). RNoC cung cấp khả năng tự thích ứng với sự thay đổi cấu hình mạng khi có một bộ định tuyến rời khỏi mạng mà vẫn bảo đảm chức năng truyền thông ổn định cho toàn hệ thống. Bẳng cách thay đổi thông tin tại trường tuyến để linh hoạt đường đi của thông tin khi hướng đi cố định bị chặn, giải pháp cập nhật định tuyến hạn chế được tác động nhiều giao tác truyền thông và tối ưu các chi phí thực thi trên chip. Để thực hiện hoạt động cập nhật thông tin định tuyến chúng tôi bổ sung một khối cổng ảo (RMport: Routing Modification) vào kiến trúc bộ định tuyến của mạng trên chip. Kiến trúc bộ định tuyến được thực hiện cho cấu trúc mạng dạng lưới 2D-mesh với giải thuật định tuyến tĩnh XY tại nguồn. Bộ định tuyến mạng trên chip tái cấu hình hoạt động ở hai chế độ: chế độ bình thường và chế độ tái cấu hình. Trong chế độ bình thường, bộ định tuyến đáp ứng yêu cầu chuyển tiếp thông tin theo đường định tuyến đã được xác định tại nguồn phát. Trong trường hợp hướng đi đến bộ định tuyến lân cận bị chặn, bộ định tuyến sẽ hoạt động ở chế độ tái cấu hình để cập nhật thông tin định tuyến thích ứng với cấu hình mạng hiện thời. Kết quả thực nghiệm được đánh giá dựa trên hiệu quả truyền thông với một số kiến trúc của một số công trình đã công bố.Van Thanh Vu Levulvt@husc.edu.vnXuan Tu Trantutx@vnu.edu.vn2016-05-23T02:26:29Z2017-01-17T02:22:01Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1560This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/15602016-05-23T02:26:29ZThiết kế và mô hình hoá bộ xử lý lô-gic mờ trong điều khiển tần số - điện ápTrong bài báo này, chúng tôi trình bày việc thiết kế một bộ điều khiển sử dụng thuật toán lô-gic mờ có khả năng dự đoán lưu lượng truyền thông của một bộ định tuyến trong mạng trên chip (NoC: Network-on-Chip). Từ đó, bộ điều khiển này sẽ tác động đến tần số và điện áp hoạt động của bộ định tuyến một cách phù hợp nhằm giảm thiểu năng lượng tiêu thụ của bộ định tuyến này theo phương pháp điều khiển tỷ lệ điện áp – tần số động (DVFS: Dynamic Voltage and Frequency Scaling) trong khi vẫn đảm bảo được hiệu năng hoạt động theo yêu cầu của bộ định tuyến. Bộ xử lý lô-gic mờ (FLP), phần lõi của thiết kế, đã được mô hình hoá bằng ngôn ngữ mô tả phần cứng VHDL. Hoạt động của bộ xử lý mờ được mô phỏng và kiểm chứng bằng phần mềm mô phỏng ModelSim của hãng Mentor Graphics.Hai Phong Phanhaiphongphan@gmail.comXuan Tu Trantutx@vnu.edu.vn2016-05-15T14:27:14Z2017-01-17T02:49:13Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1512This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/15122016-05-15T14:27:14ZRouting-path Tracking and Updating Mechanism in Reconfigurable Network-on-ChipsAs the rapid advancement in semiconductor technology leads to shrinking of transistor sizes and the integration scale is over one billion transistors, Reconfigurable Network-on-Chips becomes a new methodology providing adaptive infrastructure resources as well as flexible network protocols to adapt to dynamic environment. In this paper, we propose a routing-path tracking and updating mechanism for reconfigurable Network-on-Chips. The hardware architectures used to implement the proposed mechanism such as modified RNoC routers and Network Interfaces are introduced. With this routing-path tracking and updating mechanism, packet transmission delay can be reduced from 4.92% to 33.33% depending on the data structures.Thi Thuy Nguyenthuynguyen@vnu.edu.vnVan Thanh Vu Levulvt@husc.edu.vnKiem Hung Nguyenkiemhung@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn2016-05-14T14:44:46Z2017-01-17T02:20:44Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1511This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/15112016-05-14T14:44:46ZUltra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT ApplicationsIn this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.Duy Hieu Buihieubd@vnu.edu.vnDiego Puschinidiego.puschini@cea.frSimone Bacles-MinSimone.BACLES-MIN@cea.frEdith BeigneXuan Tu Trantutx@vnu.edu.vn2016-02-15T02:55:33Z2017-01-17T02:13:33Zhttp://eprints.uet.vnu.edu.vn/eprints/id/eprint/1484This item is in the repository with the URL: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/14842016-02-15T02:55:33ZAn Efficient Implementation of Advanced Encryption Standard on the Coarse-grained Reconfigurable ArchitectureThe Advanced Encryption Standard (AES) is currently considered as one of the best symmetric-key block ciphers. The hardware implementation of the AES for hand-held mobile devices or wireless sensor network nodes is always required to meet the strict constraints in terms of performance, power and cost. Coarse-grained reconfigurable architectures are recently proposed as the solution that provides high flexibility, high performance and low power consumption for the next-generation embedded systems. This paper presents a flexible, high-performance implementation of the AES algorithm on a coarse-grained reconfigurable architecture, called MUSRA (Multimedia Specific Reconfigurable Architecture). First, we propose a hardware-software partitioning method for mapping the AES algorithm onto the MUSRA. Second, the parallel and pipelining techniques are considered thoughtfully to increase total computing throughput by efficiently utilizing the computing resources of the MUSRA. Some optimizations at both loop transformation level and scheduling level are performed in order to make better use of instruction-, loop- and task- level parallelism. The proposed implementation has been evaluated by the cycle-accurate simulator of the MUSRA. Experimental results show that the MUSRA can be reconfigured to support both encryption and decryption with all key lengths specified in the AES standard. The performance of the AES algorithm on the MUSRA is better than that of the ADRES reconfigurable processor, Xilinx Virtex-II, and the TI C64+ DSP.Kiem Hung Nguyenkiemhung@vnu.edu.vnXuan Tu Trantutx@vnu.edu.vn