VNU-UET Repository

How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes

Tran, Xuan Tu and Durupt, Jean and Bertrand, François and Beroulle, Vincent and Robach, Chantal (2007) How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes. In: Informal Proceedings of the 12th IEEE European Test Symposium (ETS).

Available under License Creative Commons Attribution Non-commercial.

Download (1MB)


The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented.

Item Type: Conference or Workshop Item (Paper)
Subjects: Electronics and Communications
?? Electronics ??
Electronics and Communications > Electronics and Computer Engineering
?? QA75 ??
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Mr Duy-Hieu Bui
Date Deposited: 26 Jan 2011 07:23
Last Modified: 17 Jan 2017 02:43

Actions (login required)

View Item View Item