VNU-UET Repository

A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs

Nguyen, Kiem Hung and Tran, Xuan Tu (2019) A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs. Journal of Systems Architecture, 100 . pp. 101664-101677. ISSN 1383-7621

Full text not available from this repository.


This paper presents a proposal and implementation of a multi-mode full-reconfigurable router for Network-on-Chip (NoC). First, the router supports a hybrid packet-switching architecture that is dynamically reconfigurable to exchange between wormhole and virtual cut-through switching schemes at run-time. Therefore, it reaches a higher average performance than wormhole switching, while decreasing the implementation cost in comparison with the virtual cut-through switching. Second, the router is equipped a Quality-of-Services (QoS)-driven arbiter. Therefore, the proposed solution not only guarantees the guaranteed-throughput service without reserving resources but also enhances the average performance for the best-effort service by using network resources efficiently based on the priority inheritance arbitration mechanism. Third, the router is enhanced with the dynamically deadline-aware rerouting mechanism. In contention situation, the router can configure the routing computation unit to reroute the packet to another path so as to reduce the waiting interval of the blocked packets. The router was designed at the Register Transfer Level and modeled using VHDL language and then synthesized with Xilinx Virtex-7 FPGA technology. The experimental results prove that the proposed router is reliable and can improve the average performance of different QoS loads significantly compared with the generic routers while the area and power overhead are acceptable.

Item Type: Article
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Scopus-indexed journals
ISI-indexed journals
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 08 Nov 2019 03:20
Last Modified: 08 Nov 2019 03:20

Actions (login required)

View Item View Item