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A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications

Dong, Pham Khoi and Nguyen, Kiem Hung and Tran, Xuan Tu (2019) A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications. In: 2019 19th International Symposium on Communications and Information Technologies (ISCIT), 25-27 September 2019, Ho Chi Minh city.

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In this paper, we propose a high-throughput and low-latency AES architecture for wideband and real-time applications such as surveillance cameras, video conference, motion detection, IoT gateways, data store encryption… Our design uses an outer round pipeline technique to achieve high throughput. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. The implementation results show that the proposed architecture achieves a throughput of 111.3Gbps and a latency of 12.6ns at the maximum operating frequency of 870MHz. With the same 45nm CMOS technology, our design has area efficiency (2.4 times) and energy efficiency (4.7 times) higher than other related works.

Item Type: Conference or Workshop Item (Paper)
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 06 Dec 2019 08:30
Last Modified: 06 Dec 2019 08:30

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