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A Survey of High-Efficient CABAC Hardware Implementations in HEVC Standard

Tran, Dinh Lam and Pham, Viet Huong and Nguyen, Kiem Hung and Tran, Xuan Tu (2019) A Survey of High-Efficient CABAC Hardware Implementations in HEVC Standard. VNU Journal of Computer Science and Communication Engineering, 35 (2). pp. 1-21. ISSN 0866-8612

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High-Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is the newest video coding standard developed to address the increasing demand for higher resolutions and frame rates. In comparison to its predecessor H.264/AVC, HEVC achieved almost double of compression performance that is capable to process high quality video sequences (UHD 4K, 8K; high frame rates) in a wide range of applications. CABAC is the only entropy coding method in HEVC, whose principal algorithm is inherited from its predecessor. However, several aspects of the method that exploits it in HEVC are different, thus HEVC CABAC supports better coding efficiency. Effectively, pipeline and parallelism in CABAC hardware architectures are prospective methods in the implementation of high performance CABAC designs. However, high data dependence and serial nature of bin-to-bin processing in CABAC algorithm pose many challenges for hardware designers. This paper provides an overview of CABAC hardware implementations for HEVC targeting high quality, low power video applications, addresses challenges of exploiting it in different application scenarios and then recommends several predictive research trends in the future.

Item Type: Article
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 06 Dec 2019 08:47
Last Modified: 06 Dec 2019 08:47

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