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An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder

Tran, Dinh Lam and Tran, Xuan Tu and Bui, Duy Hieu and Pham, Cong Kha (2020) An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder. Electronics, 9 (4). p. 684. ISSN 2079-9292

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HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.

Item Type: Article
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Information Technology (IT)
Scopus-indexed journals
ISI-indexed journals
Divisions: Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 24 Apr 2020 04:18
Last Modified: 24 Apr 2020 04:18

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