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A Hardware Architecture for Intra Prediction in H.264/AVC Encoder

Bui, Duy Hieu and Tran, Van Huan and Nguyen, Van Mien and Ngo, Duc Hoang and Tran, Xuan Tu (2012) A Hardware Architecture for Intra Prediction in H.264/AVC Encoder. In: 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), 13-15 August 2012, Danang, Vietnam.

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MPEG-4 AVC, so called H.264/AVC, is the latest video compression standard focusing on network transport and storage of digital multimedia. In H.264 system, the intra prediction module is one of the most essential parts and it is different from the previous video compression standards. With the new prediction techniques, intra prediction in H.264 improves the bit rate but it also increases the memory bandwidth and the computational complexity with many prediction modes. In this work, the intra prediction procedure is fully analyzed. Based on the analysis, a hardware architecture for intra prediction focused on main profile of H.264/AVC is proposed. The proposed architecture uses an adder tree to generate the predicted pixels for all prediction modes. The cost calculation method is Sum of Absolute Transformed Difference (SATD) and mode decision is the full search scheme. The proposed architecture can do intra prediction of an HDTV input in real-time and it is successfully simulated using Modelsim and synthesized using Xilinx ISE 10.1.

Item Type: Conference or Workshop Item (Paper)
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 02 Nov 2012 02:28
Last Modified: 17 Jan 2017 02:34

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