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H.264/AVC Hardware Encoders and Low-Power Features

Nguyen, Ngoc-Mai and Beigne, Edith and Lesecq, Suzanne and Bui, Duy Hieu and Dang, Nam Khanh and Tran, Xuan Tu (2014) H.264/AVC Hardware Encoders and Low-Power Features. In: 2014: the 12th of the biennial IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), 17-20 November 2014, Okinawa, Japan.

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Because of significant bit rate reduction in comparison to the previous video compression standards, the H.264/AVC has been successfully used in a wide range of applications. In hardware design for H.264/AVC video encoders, power reduction is currently a tremendous challenge. This paper presents a survey of different H.264/AVC hardware encoders focusing on power features and power reduction techniques to be applied. A new H.264/AVC hardware encoder, named VENGME, is proposed. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at RTL level, is 19.1mW.

Item Type: Conference or Workshop Item (Paper)
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 31 Dec 2014 05:14
Last Modified: 17 Jan 2017 02:22

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