TY  - CONF
ID  - SisLab11
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/11/
A1  - Thonnart, Yvain
A1  - Tran, Xuan Tu
A1  - Vivet, Pascal
A1  - Beigne, Edith
A1  - Clermidy, Fabien
A1  - Durupt, Jean
Y1  - 2009/11//
N2  - The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on-Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.
TI  - An Asynchronous Low-Power Innovative Network-on-Chip including Design-for-Test capabilities
M2  - Haiphong, Vietnam
AV  - public
T2  - 2009 International Conference on Advanced Technologies for Communications
ER  -