eprintid: 11
rev_number: 23
eprint_status: archive
userid: 1
dir: disk0/00/00/00/11
datestamp: 2010-01-29 09:42:56
lastmod: 2017-01-17 02:39:55
status_changed: 2010-01-29 09:42:56
type: conference_item
metadata_visibility: show
item_issues_count: 0
creators_name: Thonnart, Yvain
creators_name: Tran, Xuan Tu
creators_name: Vivet, Pascal
creators_name: Beigne, Edith
creators_name: Clermidy, Fabien
creators_name: Durupt, Jean
creators_id: tutx@vnu.edu.vn
title: An Asynchronous Low-Power Innovative Network-on-Chip including Design-for-Test capabilities
ispublished: pub
subjects: AC
subjects: ECE
subjects: Electronics
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
abstract: The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on-Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.
date: 2009-11
date_type: published
contact_email: tutx@vnu.edu,vn
full_text_status: public
pres_type: paper
publication: Proceedings of the 2009 International Conference on Advanced Technologies for Communications
event_title: 2009 International Conference on Advanced Technologies for Communications
event_location: Haiphong, Vietnam
event_type: conference
refereed: TRUE
citation:   Thonnart, Yvain and Tran, Xuan Tu and Vivet, Pascal and Beigne, Edith and Clermidy, Fabien and Durupt, Jean  (2009) An Asynchronous Low-Power Innovative Network-on-Chip including Design-for-Test capabilities.  In: 2009 International Conference on Advanced Technologies for Communications, Haiphong, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/11/1/ATC2009-submitted-final-20090827.pdf