eprintid: 13
rev_number: 14
eprint_status: archive
userid: 1
dir: disk0/00/00/00/13
datestamp: 2010-01-29 09:48:20
lastmod: 2017-01-17 02:40:36
status_changed: 2010-01-29 09:48:20
type: conference_item
metadata_visibility: show
item_issues_count: 0
creators_name: Tran, Xuan Tu
creators_name: Thonnart, Yvain
creators_name: Durupt, Jean
creators_name: Beroulle, Vincent
creators_name: Robach, Chantal
creators_id: tutx@vnu.edu.vn
title: A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application
ispublished: pub
subjects: AC
subjects: ECE
subjects: Electronics
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
note: <span class='textit'>Oral presentation</span>
date: 2008-04
official_url: http://async.org.uk/nocs2008/
full_text_status: none
pres_type: paper
place_of_pub: New Type Upon, UK
event_title: Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chips (NOCS 2008)
event_type: conference
refereed: TRUE
citation:   Tran, Xuan Tu and Thonnart, Yvain and Durupt, Jean and Beroulle, Vincent and Robach, Chantal  (2008) A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.  In: Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chips (NOCS 2008).