relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1511/
title: Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications
creator: Bui, Duy Hieu
creator: Puschini, Diego
creator: Bacles-Min, Simone
creator: Beigne, Edith
creator: Tran, Xuan Tu
subject: Electronics and Communications
subject: Electronics and Computer Engineering
description: In this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.
date: 2016-05
type: Conference or Workshop Item
type: PeerReviewed
format: application/pdf
language: en
identifier: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1511/1/ICICDT2016_draft_BUIDuy-Hieu-2016-05-15_final.pdf
identifier:   Bui, Duy Hieu and Puschini, Diego and Bacles-Min, Simone and Beigne, Edith and Tran, Xuan Tu  (2016) Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications.  In: The 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam.