TY  - CONF
ID  - SisLab1511
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1511/
A1  - Bui, Duy Hieu
A1  - Puschini, Diego
A1  - Bacles-Min, Simone
A1  - Beigne, Edith
A1  - Tran, Xuan Tu
Y1  - 2016/05//
N2  - In this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.
TI  - Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications
M2  - Ho Chi Minh city, Vietnam
AV  - public
T2  - The 2016 IEEE International Conference on Integrated Circuit Design and Technology
ER  -