TY  - CONF
ID  - SisLab1512
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1512/
A1  - Nguyen, Thi Thuy
A1  - Le, Van Thanh Vu
A1  - Nguyen, Kiem Hung
A1  - Tran, Xuan Tu
Y1  - 2016/06/27/
N2  - As the rapid advancement in semiconductor technology leads to shrinking of transistor sizes and the integration scale is over one billion transistors, Reconfigurable Network-on-Chips becomes a new methodology providing adaptive infrastructure resources as well as flexible network protocols to adapt to dynamic environment. In this paper, we propose a routing-path tracking and updating mechanism for reconfigurable Network-on-Chips. The hardware architectures used to implement the proposed mechanism such as modified RNoC routers and Network Interfaces are introduced. With this routing-path tracking and updating mechanism, packet transmission delay can be reduced from 4.92% to 33.33% depending on the data structures.
TI  - Routing-path Tracking and Updating Mechanism in Reconfigurable Network-on-Chips
M2  - Ho Chi Minh city, Vietnam
AV  - public
T2  - The 2016 IEEE International Conference on Integrated Circuit Design and Technology
ER  -