eprintid: 1512
rev_number: 12
eprint_status: archive
userid: 4
dir: disk0/00/00/15/12
datestamp: 2016-05-15 14:27:14
lastmod: 2017-01-17 02:49:13
status_changed: 2016-05-15 14:27:14
type: conference_item
metadata_visibility: show
creators_name: Nguyen, Thi Thuy
creators_name: Le, Van Thanh Vu
creators_name: Nguyen, Kiem Hung
creators_name: Tran, Xuan Tu
creators_id: thuynguyen@vnu.edu.vn
creators_id: vulvt@husc.edu.vn
creators_id: kiemhung@vnu.edu.vn
creators_id: tutx@vnu.edu.vn
title: Routing-path Tracking and Updating Mechanism in Reconfigurable Network-on-Chips
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
abstract: As the rapid advancement in semiconductor technology leads to shrinking of transistor sizes and the integration scale is over one billion transistors, Reconfigurable Network-on-Chips becomes a new methodology providing adaptive infrastructure resources as well as flexible network protocols to adapt to dynamic environment. In this paper, we propose a routing-path tracking and updating mechanism for reconfigurable Network-on-Chips. The hardware architectures used to implement the proposed mechanism such as modified RNoC routers and Network Interfaces are introduced. With this routing-path tracking and updating mechanism, packet transmission delay can be reduced from 4.92% to 33.33% depending on the data structures.
date: 2016-06-27
date_type: published
full_text_status: public
pres_type: paper
event_title: The 2016 IEEE International Conference on Integrated Circuit Design and Technology
event_location: Ho Chi Minh city, Vietnam
event_dates: 27-29 June 2016
event_type: conference
refereed: TRUE
referencetext: [1] Agarwal, C. Iskander, R. Shankar. Survey of Network on Chip (NoC) architectures & contributions. Journal of engineering, Computing and Architecture, vol. 3, no. 1, pp. 21-27, 2009.
[2] R. Dafali, J. P. Diguet, M. Sevaux. Key Research Issues for Reconfigurable Network-on-Chip. International Conference on Reconfigurable Computing and FPGAs, pp. 181-186, 2008.
[3] Xuan-Tu Tran, et al. Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. IET Journal on Computers and Digital Techniques, Volume 3, Issue 5, pp. 487-500, Sept. 2009.
[4] M. B. Stensgaard, J. Spars, and x0F, "ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology." pp. 55-64, 2008.
[5] M. A. A. Faruque, T. Ebi, and J. Henkel, "Configurable links for runtime adaptive on-chip communication." pp. 256-261, 2009.
[6] L.-V. Thanh-Vu, X.-T. Tran. High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router. REV Journal on Electronics and Communications, vol. 4, pp. 68-74, 2014.
[7] Z. A. M. Adnan Mahmood, “Design and prototype of resource network interfaces for netwok on chip,” Master of Science 2009.
citation:   Nguyen, Thi Thuy and Le, Van Thanh Vu and Nguyen, Kiem Hung and Tran, Xuan Tu  (2016) Routing-path Tracking and Updating Mechanism in Reconfigurable Network-on-Chips.  In: The 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1512/1/ICICDT2016_thuynt_ver06-TXT.pdf