relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1565/
title: Sub-100nm ferroelectric-gate thin film transistor fabricated by two-step patterning method
creator: Do, Hong Minh
creator: Pham, Duc Thang
creator: Bui, Nguyen Quoc Trinh
subject: Engineering Physics
description: Ferroelectric-gate thin film transistor (FGT) which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator has attracted wide attention for the application of a new nonvolatile memory because of its prominent features such as simple device structure, high-speed operation and low power consumption. Recently, we have reported on demonstration of the of FGTs operation. However, the FGTs developed have channel lengths (LDS) more than 100 nm, which should be reduced for high-density storage in integration circuits.1-2) In this paper, we will present a new method to fabricate the sub-100 nm FGT, of which the source-drain gap would be surely created, in principle, comparing with the conventional patterning method. Electrical properties and memory functionalities of the fabricated sub-100nm FGTs will be investigated and discussed in detail.
date: 2016-03-26
type: Conference or Workshop Item
type: NonPeerReviewed
format: application/pdf
language: en
identifier: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1565/1/Presentation-DHMinh.pdf
identifier:   Do, Hong Minh and Pham, Duc Thang and Bui, Nguyen Quoc Trinh  (2016) Sub-100nm ferroelectric-gate thin film transistor fabricated by two-step patterning method.  In: SW4PHD: the 2016 Scientific Workshop for PhD Students, 26 March 2016, Hanoi.