eprintid: 1565
rev_number: 11
eprint_status: archive
userid: 243
dir: disk0/00/00/15/65
datestamp: 2016-05-23 02:17:06
lastmod: 2016-05-23 02:19:58
status_changed: 2016-05-23 02:17:06
type: conference_item
metadata_visibility: show
creators_name: Do, Hong Minh
creators_name: Pham, Duc Thang
creators_name: Bui, Nguyen Quoc Trinh
creators_id: pdthang@vnu.edu.vn
creators_id: trinhbnq@vnu.edu.vn
title: Sub-100nm ferroelectric-gate thin film transistor fabricated by two-step patterning method
ispublished: pub
subjects: Phys
divisions: fac_physic
abstract: Ferroelectric-gate thin film transistor (FGT) which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator has attracted wide attention for the application of a new nonvolatile memory because of its prominent features such as simple device structure, high-speed operation and low power consumption. Recently, we have reported on demonstration of the of FGTs operation. However, the FGTs developed have channel lengths (LDS) more than 100 nm, which should be reduced for high-density storage in integration circuits.1-2) In this paper, we will present a new method to fabricate the sub-100 nm FGT, of which the source-drain gap would be surely created, in principle, comparing with the conventional patterning method. Electrical properties and memory functionalities of the fabricated sub-100nm FGTs will be investigated and discussed in detail.
date: 2016-03-26
date_type: published
full_text_status: public
pres_type: poster
event_title: SW4PHD: the 2016 Scientific Workshop for PhD Students
event_location: Hanoi
event_dates: 26 March 2016
event_type: workshop
refereed: FALSE
citation:   Do, Hong Minh and Pham, Duc Thang and Bui, Nguyen Quoc Trinh  (2016) Sub-100nm ferroelectric-gate thin film transistor fabricated by two-step patterning method.  In: SW4PHD: the 2016 Scientific Workshop for PhD Students, 26 March 2016, Hanoi.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/1565/1/Presentation-DHMinh.pdf