eprintid: 1824
rev_number: 7
eprint_status: archive
userid: 5
dir: disk0/00/00/18/24
datestamp: 2016-07-18 03:17:20
lastmod: 2016-07-18 03:18:12
status_changed: 2016-07-18 03:17:20
type: article
metadata_visibility: show
creators_name: Do, Hong Minh
creators_name: Bui, Nguyen Quoc Trinh
creators_id: trinhbnq@vnu.edu.vn
title: Sub-100 nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO2/Si Substrate
ispublished: pub
subjects: Phys
divisions: fac_physic
abstract: Thin film transistor which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator, so-called FGT, has wide attention for the application of a new nonvolatile memory owing to its prominent features such as simple structure, high speed and low power consumption. Previously, we have reported on demonstration of the FGTs operation, but the ones developed have channel lengths (LDS) more than 100 nm, which should be reduced for high-density storage in integration circuits. In this work, a new technique has been proposed to fabricate the sub-100 nm FGT using low-temperature PZT thin film, whose source-drain gap would be mainly created from electron beam lithography, dry etching and ashing. With the new technique, the memory functionality of the fabricated sub-100 nm FGTs are comparable with that of the sub-μm sized FGT. In particular, the ON/OFF current ratio is about 104–105, the memory window is 2.0, 1.8 and 1.7 V, and the field-effect mobility is 0.12, 0.07 and 0.16 cm2V−1s−1 for the LDS of 100, 50, and 30 nm, respectively.
date: 2015
date_type: published
official_url: DOI:10.1080/07315171.2015.1026215
full_text_status: none
publication: Ferroelectrics Letters Section
volume: 42
number: 1-3
refereed: TRUE
citation:   Do, Hong Minh and Bui, Nguyen Quoc Trinh  (2015) Sub-100 nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO2/Si Substrate.  Ferroelectrics Letters Section, 42  (1-3).