@article{SisLab22,
          volume = {3},
          number = {5},
           month = {September},
          author = {Xuan Tu Tran and Yvain Thonnart and Jean Durupt and Vincent Beroulle and Chantal Robach},
           title = {Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and
Application},
       publisher = {IET},
            year = {2009},
         journal = {IET Computers \& Digital Techniques},
             doi = {10.1049/iet-cdt.2008.0072},
           pages = {487--500},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/22/},
        abstract = {Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the
asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents
the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86\%) for single stuck-at fault models.}
}