relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/22/
title: Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and  Application
creator: Tran, Xuan Tu
creator: Thonnart, Yvain
creator: Durupt, Jean
creator: Beroulle, Vincent
creator: Robach, Chantal
subject: Electronics and Communications
subject: Electronics and Computer Engineering
subject: ISI-indexed journals
description: Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the  asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents  the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
publisher: IET
date: 2009-09
type: Article
type: PeerReviewed
format: application/pdf
language: en
identifier: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/22/1/Design-for-test_approach_of_an_asynchronous_network-on-chip_architecture-published-IET.pdf
identifier:   Tran, Xuan Tu and Thonnart, Yvain and Durupt, Jean and Beroulle, Vincent and Robach, Chantal  (2009) Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.  IET Computers & Digital Techniques, 3  (5).   pp. 487-500.  ISSN 1751-8601     
relation: 10.1049/iet-cdt.2008.0072