TY  - JOUR
ID  - SisLab22
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/22/
IS  - 5
A1  - Tran, Xuan Tu
A1  - Thonnart, Yvain
A1  - Durupt, Jean
A1  - Beroulle, Vincent
A1  - Robach, Chantal
Y1  - 2009/09//
N2  - Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the
asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents
the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
PB  - IET
JF  - IET Computers & Digital Techniques
VL  - 3
SN  - 1751-8601
TI  - Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and
Application
SP  - 487
AV  - public
EP  - 500
ER  -