%A Xuan Tu Tran
%A Yvain Thonnart
%A Jean Durupt
%A Vincent Beroulle
%A Chantal Robach
%J IET Computers & Digital Techniques
%T Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and
Application
%X Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the
asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents
the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
%N 5
%P 487-500
%V 3
%D 2009
%I IET
%R 10.1049/iet-cdt.2008.0072
%L SisLab22