eprintid: 22
rev_number: 25
eprint_status: archive
userid: 1
dir: disk0/00/00/00/22
datestamp: 2011-01-26 05:06:05
lastmod: 2017-01-17 02:17:47
status_changed: 2012-10-31 05:01:25
type: article
metadata_visibility: show
item_issues_count: 0
creators_name: Tran, Xuan Tu
creators_name: Thonnart, Yvain
creators_name: Durupt, Jean
creators_name: Beroulle, Vincent
creators_name: Robach, Chantal
creators_id: tutx@vnu.edu.vn
title: Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and
Application
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
subjects: isi
divisions: fac_fet
divisions: lab_sis
abstract: Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the
asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents
the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
date: 2009-09
date_type: published
publisher: IET
id_number: 10.1049/iet-cdt.2008.0072
contact_email: tutx@vnu.edu.vn
full_text_status: public
publication: IET Computers & Digital Techniques
volume: 3
number: 5
pagerange: 487-500
refereed: TRUE
issn: 1751-8601
citation:   Tran, Xuan Tu and Thonnart, Yvain and Durupt, Jean and Beroulle, Vincent and Robach, Chantal  (2009) Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.  IET Computers & Digital Techniques, 3  (5).   pp. 487-500.  ISSN 1751-8601     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/22/1/Design-for-test_approach_of_an_asynchronous_network-on-chip_architecture-published-IET.pdf