%A Thanh Tung Bui
%A Xiaojin Cheng
%A Naoya Watanabe
%A Fumiki Kato
%A Katsuya Kikuchi
%A Masahiro Aoyagi
%T A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration
%D 2016
%R doi:10.1109/ECTC.2016.344
%P 2182-2187
%L SisLab2326
%B 2016 IEEE 66th Electronic Components and Technology Conference (ECTC)