eprintid: 2326
rev_number: 8
eprint_status: archive
userid: 270
dir: disk0/00/00/23/26
datestamp: 2016-12-28 14:40:04
lastmod: 2016-12-28 14:40:04
status_changed: 2016-12-28 14:40:04
type: conference_item
metadata_visibility: show
creators_name: Bui, Thanh Tung
creators_name: Cheng, Xiaojin
creators_name: Watanabe, Naoya
creators_name: Kato, Fumiki
creators_name: Kikuchi, Katsuya
creators_name: Aoyagi, Masahiro
creators_id: tungbt@vnu.edu.vn
title: A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration
ispublished: pub
subjects: ECE
divisions: fac_fet
date: 2016
date_type: published
official_url: http://doi.org/10.1109/ECTC.2016.344
id_number: doi:10.1109/ECTC.2016.344
full_text_status: none
pres_type: poster
pagerange: 2182-2187
event_title: 2016 IEEE 66th Electronic Components and Technology Conference (ECTC)
event_dates: 2016
event_type: conference
refereed: TRUE
book_title: 2016 IEEE 66th Electronic Components and Technology Conference (ECTC)
citation:   Bui, Thanh Tung and Cheng, Xiaojin and Watanabe, Naoya and Kato, Fumiki and Kikuchi, Katsuya and Aoyagi, Masahiro  (2016) A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration.  In: 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016.