relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/24/
title: How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes
creator: Tran, Xuan Tu
creator: Durupt, Jean
creator: Bertrand, François
creator: Beroulle, Vincent
creator: Robach, Chantal
subject: Electronics and Communications
subject: Electronics and Computer Engineering
description: The Network-on-Chip (NoC) paradigm is currently known  as an alternative solution for the on chip communication in  the next SoC generation, especially, asynchronous NoCs. One  of the challenges for asynchronous NoC-based systems design  is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented.
date: 2007-05
type: Conference or Workshop Item
type: PeerReviewed
format: application/pdf
language: en
rights: cc_by_nc
identifier: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/24/1/ETS2007_Tran_Howto_Implement_an_Asynchronous_Test_Wrapper.pdf
identifier:   Tran, Xuan Tu and Durupt, Jean and Bertrand, François and Beroulle, Vincent and Robach, Chantal  (2007) How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes.  In: Informal Proceedings of the 12th IEEE European Test Symposium (ETS).