TY  - CONF
CY  - Freiburg, Germany
ID  - SisLab24
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/24/
A1  - Tran, Xuan Tu
A1  - Durupt, Jean
A1  - Bertrand, François
A1  - Beroulle, Vincent
A1  - Robach, Chantal
Y1  - 2007/05//
N2  - The Network-on-Chip (NoC) paradigm is currently known
as an alternative solution for the on chip communication in
the next SoC generation, especially, asynchronous NoCs. One
of the challenges for asynchronous NoC-based systems design
is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented.
TI  - How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes
SP  - 29
AV  - public
EP  - 34
T2  - Informal Proceedings of the 12th IEEE European Test Symposium (ETS)
ER  -