eprintid: 24
rev_number: 18
eprint_status: archive
userid: 1
dir: disk0/00/00/00/24
datestamp: 2011-01-26 07:23:58
lastmod: 2017-01-17 02:43:09
status_changed: 2011-01-26 07:23:58
type: conference_item
metadata_visibility: show
item_issues_count: 0
creators_name: Tran, Xuan Tu
creators_name: Durupt, Jean
creators_name: Bertrand, François
creators_name: Beroulle, Vincent
creators_name: Robach, Chantal
creators_id: tutx@vnu.edu.vn
title: How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes
ispublished: pub
subjects: ECE
subjects: Electronics
subjects: ElectronicsandComputerEngineering
subjects: QA75
divisions: fac_fet
divisions: lab_sis
abstract: The Network-on-Chip (NoC) paradigm is currently known
as an alternative solution for the on chip communication in
the next SoC generation, especially, asynchronous NoCs. One
of the challenges for asynchronous NoC-based systems design
is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented.
date: 2007-05
date_type: published
full_text_status: public
pres_type: paper
place_of_pub: Freiburg, Germany
pagerange: 29-34
event_title: Informal Proceedings of the 12th IEEE European Test Symposium (ETS)
event_type: conference
refereed: TRUE
citation:   Tran, Xuan Tu and Durupt, Jean and Bertrand, François and Beroulle, Vincent and Robach, Chantal  (2007) How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes.  In: Informal Proceedings of the 12th IEEE European Test Symposium (ETS).     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/24/1/ETS2007_Tran_Howto_Implement_an_Asynchronous_Test_Wrapper.pdf