TY  - JOUR
ID  - SisLab2468
UR  - https://www.jstage.jst.go.jp/article/transfun/E100.A/8/E100.A_1650/_article
IS  - 8
A1  - Tran, Xuan Tu
A1  - Nguyen, Tung
A1  - Phan, Hai Phong
A1  - Bui, Duy Hieu
Y1  - 2017/08/01/
N2  - The increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793um2 with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.
PB  - IEICE
JF  - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VL  - E100-A
SN  - 1745-1337
TI  - ?AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures
SP  - 1650
AV  - none
EP  - 1660
ER  -