@article{SisLab2621,
          volume = {40},
          number = {2013},
           title = {Interface Charge Trap Density of Solution Processed Ferroelectric Gate Thin Film Transistor Using ITO/PZT/Pt Structure},
          author = {Van Thanh Pham and Nguyen Quoc Trinh Bui and Miyasako Takaaki and Trong Tue Phan and Tokumitsu Eisuke and Shimoda Tatsuya},
            year = {2013},
           pages = {17--29},
         journal = {Ferroelectrics Letters},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/2621/},
        abstract = {The conductance method was applied to investigate the interface charge trap density
(Dit) of solution processed ferroelectric gate thin film transistor (FGT) using indium-tin
oxide (ITO)/ Pb(Zr,Ti)O3 (PZT)/Pt structure. As a result, a large value of Dit of MFS
capacitor, i.e., Pt/PZT/ITO, was estimated to be 1.2 {$\times$} 1014 eV?1 cm?2. This large Dit
means that an interface between the ITO layer and the PZT layer is imperfect and it is
one of themain reasons for the poor memory property of this FGT. By using transmission
electron microscopy (TEM), this imperfect interface was clearly observed. Thus, it is
concluded that improvement of this interface is critical for better memory performance.}
}