eprintid: 2745
rev_number: 10
eprint_status: archive
userid: 4
dir: disk0/00/00/27/45
datestamp: 2017-12-08 03:27:18
lastmod: 2017-12-08 03:27:18
status_changed: 2017-12-08 03:27:18
type: conference_item
metadata_visibility: show
creators_name: Nguyen, Quang Linh
creators_name: Tran, Dinh Lam
creators_name: Bui, Duy Hieu
creators_name: Mai, Duc Tho
creators_name: Tran, Xuan Tu
creators_id: nqlinh.95@gmail.com
creators_id: lamtdvdt@gmail.com
creators_id: hieubd@vnu.edu.vn
creators_id: maiductho071@gmail.com
creators_id: tutx@vnu.edu.vn
title: Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
abstract: The increasing amount of digital video with supreme quality requires more efficient compression. As the complexity of video coding algorithm is rising, there are more demands for hardware accelerators and customized hardware. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coding method adopted in the latest video compression standard, High Efficiency Video Coding (HEVC). Binary Arithmetic Encoder (BAE) is an essential component in CABAC, where the compression process happens. Because of the high data dependency and sequential coding characteristic, it is challenging to parallelize BAE. In this work, we proposed a low-cost and high-throughput hardware architecture for one core of BAE in HEVC. Our 4-stage pipelined BAE architecture is capable of processing one regular bin and up to 4 bypass bins per clock cycle with 30% reduction in terms of area when compared with the designs for one-core CABAC architecture. The design can compress an average of 1.4 bins per cycle. It achieves a throughput of 1 Gbin/s at the maximum operating frequency of 810 MHz with the area of 2.2 kGEs and the power consumption of 2.0 mW in Nangate 45nm technology.
date: 2017-10-06
date_type: published
full_text_status: public
pres_type: paper
pagerange: 82-87
event_title: The 7th International Conference on Integrated Circuits, Design, and Verification (ICDV)
event_location: Hanoi, Vietnam
event_dates: 5-6 October 2017
event_type: conference
refereed: TRUE
citation:   Nguyen, Quang Linh and Tran, Dinh Lam and Bui, Duy Hieu and Mai, Duc Tho and Tran, Xuan Tu  (2017) Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing.  In: The 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 5-6 October 2017, Hanoi, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/2745/1/bae_BUIDuyHieu-2017-08-22_TXT_removed_trackchanges.pdf