relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/3006/
title: Architecture and Design Methodology for Highly-Reliable TSV-NoC Systems
creator: Dang, Nam Khanh
creator: Abdallah, Abderazek Ben
subject: Electronics and Communications
subject: Electronics and Computer Engineering
description: During the past few decades, a lot of research has been focusing on Three-dimensional  Networks-on-Chips (3D-NoCs) as an auspicious solution to alleviate the interconnect bottleneck  and reduce the power consumption in current System-on-Chips (SoCs) designs.  However, 3D-NoC systems are becoming susceptible to a variety of faults caused by  crosstalk, radiation, oxide breakdown, and so on. As a result, a simple failure in a single  transistor caused by one of these factors may compromise the entire system reliability  where the failure can be illustrated in corrupted message delivery, time requirement unsatisfactory,  or even sometimes the whole system collapse. This chapter presents a detailed faults/defects analysis and an efficient reliability assessment method to approximate the lifetime reliability of a NoC system. Also, this chapter presents an architecture and hardware design of a fault-tolerant TSV based 3D-NoC system which can handle major failures (i.e., hard-faults, soft-errors and TSV-defects) that can occur in TSV-based 3D-NoC systems.
publisher: Nova Science Publishers
date: 2018-02
type: Book Section
type: PeerReviewed
identifier:   Dang, Nam Khanh and Abdallah, Abderazek Ben  (2018) Architecture and Design Methodology for Highly-Reliable TSV-NoC Systems.   In:  Horizons in Computer Science Research.   Nova Science Publishers, pp. 199-246.  ISBN 978-1-53613-327-1     
relation: https://www.novapublishers.com/catalog/product_info.php?products_id=64154