%0 Conference Paper
%A Abdallah, Abderazek Ben
%A Dang, Nam Khanh
%A Okuyama, Yuichi
%B Sciences and Techniques of Automatic Control and Computer Engineering (STA), 2017 18th International Conference on
%C Monastir, Tunisia
%D 2017
%F SisLab:3008
%T A Low-overhead Fault tolerant Technique for TSV-based Interconnects in 3D-IC Systems
%U https://eprints.uet.vnu.edu.vn/eprints/id/eprint/3008/
%X 3D-Network-on-Chips (3D-NoCs) are considered as one of the most advanced and auspicious communication methodologies for future IC designs by exploiting the benefits of Network-on-Chips (NoCs) and 3D-Integrated Circuits (3D-ICs). However, their reliability still remains a major problem due to the vulnerability of Through Silicon Vias (TSVs). Because most of the existing techniques rely on correcting the TSV defects by using redundancy or employing routing algorithms, the TSV-cluster defect tolerances encounter costly area and power consumption penalties. In order to solve this issue, we propose a highly scalable and low-overhead TSV management for 3D-NoC systems where the TSVs of a router can be utilized by its neighbors and an adaptive online algorithm is also performed to assist. With this proposal, we aim to maintain a graceful performance for 3D-NoCs without the need for redundant links or employing routing algorithms.