%0 Conference Paper
%A Dang, Nam Khanh
%A Meyer, Michael
%A Ahmed, Akram Ben
%A Abdallah, Abderazek Ben
%A Tran, Xuan Tu
%B IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
%C Bangkok
%D 2019
%F SisLab:3640
%T 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults
%U https://eprints.uet.vnu.edu.vn/eprints/id/eprint/3640/
%X —Through-Silicon-Via (TSV) is one of the most  promising technologies to realize 3D Integrated Circuits (3D-  ICs). However, the reliability issues due to the low yield rates,  the sensitivity to thermal hotspots and stress issues due to the  difference in temperature between layers are preventing TSV-  based 3D-ICs from being widely and efficiently used. Due to  defect clustering, 3D-ICs could have multiple defects in the same  region which cannot be detected by using error correction codes  while dedicated testing could take a significant number of testing  cycles. This paper presents a 2D Parity Product Code (2D-PPC)  with the ability to correct one fault and detect, at least, two  faults. With the extension using Orthogonal Latin Square, 2D-  PPC could detect multiple defects while reasonably increasing  the area cost and latency.