eprintid: 37
rev_number: 14
eprint_status: archive
userid: 4
dir: disk0/00/00/00/37
datestamp: 2012-11-01 08:18:46
lastmod: 2017-01-17 02:34:03
status_changed: 2012-11-01 08:18:46
type: conference_item
metadata_visibility: show
creators_name: Le-Van, Thanh Vu
creators_name: Tran, Xuan Tu
creators_name: Ngo, Dien Tap
creators_id: vulvt@husc.edu.vn
creators_id: tutx@vnu.edu.vn
creators_id: tapnd@vnu.edu.vn
corp_creators: VNU University of Engineering and Technology
corp_creators: VNU University of Engineering and Technology
title: Simulation and Performance Evaluation of a Network-on-Chip Architecture based on SystemC
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
note: ISBN: 978-1-4673-4350-3
abstract: The Network-on-Chip (NoC) paradigm has been recently known as a competitive on-chip communication solution for large complex systems such as multi-core and/or many-core systems thanks to its advantages. However, one of the main challenging issues for NoC design is that the network performance should be rapidly and early pre-proved for target applications. 

In this paper, we present a NoC simulation and evaluation platform allowing designers to simulate and evaluate the NoC performance with different network configuration parameters. The proposed platform has been implemented in SystemC to be easily modified to adapt different simulation strategies and to save the simulation time. With this platform, designers can deal with: (i) configuring the network topology, flow control mechanisms and routing algorithm; (ii) configuring various regular and application specific traffic patterns; and (iii) simulating and analyzing the network performance with the assigned traffic patterns in terms of latency and throughput. Obtained results with a 4x4 2D-mesh NoC architecture will be presented and discussed in this paper to demonstrate the proposed platform. 
date: 2012-10-12
date_type: published
official_url: http://dx.doi.org/10.1109/ATC.2012.6404252
contact_email: tutx@vnu.edu.vn
full_text_status: public
pres_type: paper
pagerange: 170-175
event_title: The 2012 International Conference on Advanced Technologies for Communications
event_location: Hanoi, Vietnam
event_dates: 12-15 October 2012
event_type: conference
refereed: TRUE
related_url_url: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6404252
projects: QGDA.10.02
citation:   Le-Van, Thanh Vu and Tran, Xuan Tu and Ngo, Dien Tap  (2012) Simulation and Performance Evaluation of a Network-on-Chip Architecture based on SystemC.  In: The 2012 International Conference on Advanced Technologies for Communications, 12-15 October 2012, Hanoi, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/37/1/Id138_bare_conf.pdf