@inproceedings{SisLab3723,
       booktitle = {IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)},
           month = {November},
           title = {A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization},
          author = {Ngo Doanh Nguyen and Duy Hieu Bui and Xuan Tu Tran},
            year = {2019},
           pages = {33--36},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/3723/},
        abstract = {Histogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 110kb SRAMs.}
}