eprintid: 3723
rev_number: 5
eprint_status: archive
userid: 267
dir: disk0/00/00/37/23
datestamp: 2019-12-06 07:41:03
lastmod: 2019-12-06 07:41:03
status_changed: 2019-12-06 07:41:03
type: conference_item
succeeds: 3720
metadata_visibility: show
creators_name: Nguyen, Ngo Doanh
creators_name: Bui, Duy Hieu
creators_name: Tran, Xuan Tu
creators_id: doanh.nn.97@gmail.com
creators_id: hieubd@vnu.edu.vn
creators_id: tutx@vnu.edu.vn
title: A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization
ispublished: pub
subjects: ElectronicsandComputerEngineering
divisions: lab_sis
divisions: fac_fet
abstract: Histogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 110kb SRAMs.
date: 2019-11-11
date_type: published
full_text_status: none
pres_type: paper
pagerange: 33-36
event_title: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
event_location: Bangkok
event_dates: 11-14 November 2019
event_type: conference
refereed: TRUE
citation:   Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu  (2019) A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization.  In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 11-14 November 2019, Bangkok.