TY  - CONF
ID  - SisLab3726
UR  - http://dx.doi.org/10.1109/ISCIT.2019.8905235
A1  - Dong, Pham Khoi
A1  - Nguyen, Kiem Hung
A1  - Tran, Xuan Tu
Y1  - 2019/10//
N2  - In this paper, we propose a high-throughput and low-latency AES architecture for wideband and real-time applications such as surveillance cameras, video conference, motion detection, IoT gateways, data store encryption? Our design uses an outer round pipeline technique to achieve high throughput. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. The implementation results show that the proposed architecture achieves a throughput of 111.3Gbps and a latency of 12.6ns at the maximum operating frequency of 870MHz. With the same 45nm CMOS technology, our design has area efficiency (2.4 times) and energy efficiency (4.7 times) higher than other related works.
TI  - A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications
SP  - 196
M2  - Ho Chi Minh city
AV  - restricted
EP  - 200
T2  - 2019 19th International Symposium on Communications and Information Technologies (ISCIT)
ER  -