@inproceedings{SisLab3727,
       booktitle = {The First International Conference of Intelligent Computing and Engineering (ICOICE)},
           month = {December},
           title = {An Efficient Implementation of LED Block Cipher on FPGA},
          author = {Mohammed Al-Shatari and Fawnizu Azmadi Hussin and Azrina Abd Aziz and Gunawan Witjaksono and Mohd Saufy Rohmad and Xuan Tu Tran},
            year = {2019},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/3727/},
        abstract = {An Iterative round-based architecture of LED block cipher is implemented in this paper. LED algorithm is available in 64-bit and 128-bit key sizes. In this paper, the focus is on the 64-bit key with 64-bit block size. This algorithm is implemented on various Field Programmable Gate Array (FPGA) devices. The design is verified on several Altera and Xilinx devices using Altera Quartus II, ModelSim and Xilinx ISE simulators. Both low-cost and high-end FPGA devices were targeted. Trade-offs between area and performance were considered, with the optimization for high performance. The throughput and maximum operating frequency are benchmarked with the existing literature and better performance is achieved. The results show high achievements in maximum operating frequency and throughput as well as reduction in area utilization compared to recent designs of round-based LED block cipher.}
}