eprintid: 40
rev_number: 12
eprint_status: archive
userid: 4
dir: disk0/00/00/00/40
datestamp: 2012-11-01 08:31:04
lastmod: 2017-01-17 02:35:10
status_changed: 2012-11-01 08:31:04
type: conference_item
metadata_visibility: show
creators_name: Le, Van Thanh Vu
creators_name: Ngo, Dien Tap
creators_name: Tran, Xuan Tu
creators_id: vulvt@husc.edu.vn
creators_id: tapnd@vnu.edu.vn
creators_id: tutx@vnu.edu.vn
corp_creators: VNU-UET
corp_creators: VNU-UET
corp_creators: VNU-UET
title: A SystemC based Simulation Platform for Network-on-Chip Architectures
ispublished: pub
subjects: ECE
subjects: Electronics
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
note: ISBN: 978-4-88552-264-2
abstract: As a promising solution for on-chip communication of large systems, the Network-on-Chip paradigm has been studied and developed by many research groups with different approaches. To bring the NoC paradigm into applications, designers have to prove their proposed NoC architectures through hardware description language (HDL) based simulations, or even through silicon test chip. Most of HDL based simulations have been implemented with low level HDLs, usually at register-transfer-level (RTL), requiring a huge amount of the simulation time. In this work, we propose a simulation platform modeled in SystemC to help designers to simulate their NoC designs with different parameters to meet the requirements of targeted applications. The proposed platform supports two-dimension topologies with a variable size of the network. The platform configuration, including platform parameters as well as communication patterns, is easily set by a shell bash. As a result, by using this platform, designers can simulate the network architecture and evaluate the network performance with a very short simulation time.
date: 2012-08-10
date_type: published
full_text_status: public
pres_type: paper
pagerange: 132-136
event_title: 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012)
event_location: Danang, Vietnam
event_dates: 13-15 August 2012
event_type: conference
refereed: TRUE
projects: QGDA.10.02
citation:   Le, Van Thanh Vu and Ngo, Dien Tap and Tran, Xuan Tu  (2012) A SystemC based Simulation Platform for Network-on-Chip Architectures.  In: 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), 13-15 August 2012, Danang, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/40/1/91.pdf