?url_ver=Z39.88-2004&rft_id=JP2019092020A&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rft.relation=https%3A%2F%2Feprints.uet.vnu.edu.vn%2Feprints%2Fid%2Feprint%2F4044%2F&rft.title=%EF%BC%93%EF%BD%84%E3%83%8D%E3%83%83%E3%83%88%E3%83%AF%E3%83%BC%E3%82%AF%E3%82%AA%E3%83%B3%E3%83%81%E3%83%83%E3%83%97%E3%81%AE%E3%81%9F%E3%82%81%E3%81%AE%EF%BD%94%EF%BD%93%EF%BD%96%E8%AA%A4%E3%82%8A%E8%80%90%E5%AE%B9%E3%83%AB%E3%83%BC%E3%82%BF%E8%A3%85%E7%BD%AE%0D%0ATSV+Error+Tolerant+Router+Device+for+3D+Network+On+Chip&rft.creator=Abdallah%2C+Abderazek+Ben&rft.creator=Dang%2C+Nam+Khanh&rft.creator=Hisada%2C+Masayuki&rft.subject=Electronics+and+Communications&rft.subject=Electronics+and+Computer+Engineering&rft.description=A+TSV+error+tolerant+router+device+for+3D+network-on-chip+is+disclosed.+In+a+TSV+error+tolerant+router+device+for+a+3D+network-on-chip+having+a+plurality+of+routers+arranged+in+each+of+a+plurality+of+layers%2C+and+routers+between+the+layers+are+connected+by+through-silicon+vias%2C+the+through-silicon+vias+are+provided.+Each+of+which+belongs+to+one+corresponding+router%2C+has+a+plurality+of+clusters+around+the+corresponding+router%2C+and+is+adjacent+to+the+corresponding+router+when+one+of+the+plurality+of+clusters+belonging+to+the+corresponding+router+is+defective+A+router+is+selected%2C+and+one+cluster+of+the+selected+router+is+replaced+in+place+of+the+defective+cluster%2C+maintaining+connectivity+between+the+layers.+%5BSelection%5D+Figure+2&rft.date=2019-06-13&rft.type=Patent&rft.type=NonPeerReviewed&rft.format=application%2Fpdf&rft.language=en&rft.identifier=https%3A%2F%2Feprints.uet.vnu.edu.vn%2Feprints%2Fid%2Feprint%2F4044%2F1%2FJP2019092020A.pdf&rft.identifier=++Univ+of+Aizu%2C+Aizu+Laboratory+Inc++(2019)+%EF%BC%93%EF%BD%84%E3%83%8D%E3%83%83%E3%83%88%E3%83%AF%E3%83%BC%E3%82%AF%E3%82%AA%E3%83%B3%E3%83%81%E3%83%83%E3%83%97%E3%81%AE%E3%81%9F%E3%82%81%E3%81%AE%EF%BD%94%EF%BD%93%EF%BD%96%E8%AA%A4%E3%82%8A%E8%80%90%E5%AE%B9%E3%83%AB%E3%83%BC%E3%82%BF%E8%A3%85%E7%BD%AE+TSV+Error+Tolerant+Router+Device+for+3D+Network+On+Chip.++JP2019092020A.+++&rft.relation=https%3A%2F%2Fpatents.google.com%2Fpatent%2FJP2019092020A%2Fen&rft.relation=JP2019092020A