TY  - PAT
ID  - SisLab4044
UR  - https://patents.google.com/patent/JP2019092020A/en
IS  - JP2019092020A
A1  - Abdallah, Abderazek Ben
A1  - Dang, Nam Khanh
A1  - Hisada, Masayuki
Y1  - 2019/06/13/
N2  - A TSV error tolerant router device for 3D network-on-chip is disclosed. In a TSV error tolerant router device for a 3D network-on-chip having a plurality of routers arranged in each of a plurality of layers, and routers between the layers are connected by through-silicon vias, the through-silicon vias are provided. Each of which belongs to one corresponding router, has a plurality of clusters around the corresponding router, and is adjacent to the corresponding router when one of the plurality of clusters belonging to the corresponding router is defective A router is selected, and one cluster of the selected router is replaced in place of the defective cluster, maintaining connectivity between the layers. [Selection] Figure 2
TI  - ?????????????????????????????
TSV Error Tolerant Router Device for 3D Network On Chip
AV  - public
EP  - 13
ER  -